Designing a new integrated circuit involves running through a well-defined sequence of design steps from the first chip specification through the microchip ready for use, said sequence being referred to as the “design flow”.
In a first design step, the desired logic functionality is described with the aid of hardware description languages such as VHDL (Very High Speed Hardware Description Language). This design level is also referred to as RTL (Register Transfer Level).
The second design step involves synthesizing the netlist. It describes the set of logic cells forming the integrated circuit, and their interconnection.
The next design step, positioning and wiring (place and route), involves positioning the logic components assigned to the logic cells on the chip surface and defining the spatial positions of the leads. This is done using so-called filler cells that fill the space required for the leads between the logic cells.
The filler cells are also referred to as positioned filler cells since they occur only in the positioned netlist which represents the end product of this design step. The positioned netlist describes the circuit layout of the integrated circuit, usually in the GDSII format (General Data Structure). The masks for the individual steps of the production process can be derived from it. Said production process can be subdivided into the so-called FEOL (Front End of Line) section and the BEOL (Back End of Line) section, the first section describing the production of the semiconductor components and the second section describing the application of the wirings or the metallization layers.
In the production process, costs and time can be saved if properties that are generally defined at the beginning of the “Design Flow” can still be corrected at a late point in time and, consequently, the iteration cycles required for the corrections remain small.
The space kept free for the leads by means of the filler cells in the place and route design step can be utilized for a different purpose. One possible procedure consists in constructing the space beneath the leads in the region of the filler cells as capacitances. Such filler cells realized as capacitances are utilized for stabilizing voltages.
The Patent Specification U.S. Pat. No. 6,321,371 B1 discloses a method for producing redesignable integrated circuits. In this case, it is possible to correct logic malfunctions of the integrated circuit, caused by an error in the design e.g. through incomplete verification, with the aid of an altered wiring.
The redesignability is achieved by filling the region of the filler cells with additional semiconductor components in the place and route design step. The latter represent replacement logic components (“spare logic gates) which are used as required—in the course of a redesign—to correct malfunctions of the logic components assigned to the logic cells. The required iteration cycle for logic correction is therefore restricted to the BEOL section of the production process.
Since the paths between the error-exhibiting logic components and the replacement logic components that effect corrective intervention are intended to be short, a maximum number of filler cells are constructed as replacement logic components. As a result, under certain circumstances, the capacitances that were present in the filler cells and were utilized for stabilizing voltages are omitted to the greatest possible extent.
The document U.S. Pat. No. 6,321,371 B1 discloses providing filler cells which represent replacement logic components of the integrated circuit. The replacement logic components are used as required in the context of a redesign of the metallization layers of the integrated circuit for the replacement of defective logic components.
The document WO 96/33495 A1 reveals the further-reaching teaching whereby such replacement logic components which are not required for the replacement of defective logic components are subsequently interconnected as backup capacitances in the redesign step. By virtue of this measure, the subsequently “superfluous” replacement logic components can also still be used expediently, namely as backup capacitances.